1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to packaging of semiconductor devices.
2. Background Art
For high power and high performance circuit applications, III-nitride transistors such as gallium nitride (GaN) field effect transistors (FETs) are often desirable for their high efficiency and high voltage operation. In particular, it is often desirable to combine such III-nitride transistors with other FETs, such as silicon FETs, to create high performance switching devices such as cascoded switches.
Unfortunately, conventional packaging integration techniques for combining III-nitride transistors with silicon FETs often negate the benefits provided by such III-nitride transistors. For example, conventional package designs may place discrete components side-by-side on a common support surface, for example a ceramic base substrate such as direct bonded copper (DBC) or a ceramic substrate on a lead-frame. The routing of current through the substrate or lead-frame undesirably increases the parasitic inductance, resistance, and thermal dissipation requirements of the package. Moreover, the side-by-side placement of package devices on the substrate undesirably increases package form factor and manufacturing cost.
Thus, a unique and cost-effective solution is needed to support the efficient design and operation of packages integrating III-nitride transistors with other FETs, such as silicon FETs.